Libero Soc

Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, advances VHDL’s verification capabilities with Active-HDL, version 13.0. This latest release introduces support for VHDL-2019 protected types with generics, composites of protected types, pointers to objects of protected types and composition with protected types.

The software developer Mentor Graphics, is pleased to announce the availability of HDL Designer Series (HDS) 2019.4 is a powerful HDL-based environment used by individual engineers and engineering teams worldwide to analyze, create and manage complex FPGA and ASIC designs.

Mentor Graphics Corp. introduced the HDL Designer Series (HDS) 2018.2, a family of point tools for complex Verilog, VHDL, or mixed-language design.

Mentor Graphics Corporation, a Siemens business, is pleased to announce the availability of Questa Formal 2021.1. This solution find obscure bugs, increasing design confidence through exhaustive analysis, before simulation test environments are available, and also boost productivity and functional verification quality by targeting verification tasks that are difficult to complete.