Monolithic Phase Locked Loops And Clock Recovery Circuits Theory And Design, Ieee Press, 1996.

This book examines the issue of design of fully integrated frequency synthesizers suitable for system-on-a-chip (SOC) processors. This book takes a more global design perspective in jointly examining the design space at the circuit level as well as at the architectural level. The coverage of the book is comprehensive and includes summary chapters on circuit theory as well as feedback control theory relevant to the operation of phase locked loops (PLLs). On the circuit level, the discussion includes low-voltage analog design in deep submicron digital CMOS processes, effects of supply noise, substrate noise, as well device noise. On the architectural level, the discussion includes PLL analysis using continuous-time as well as discre- time models, linear and nonlinear effects of PLL performance, and detailed analysis of locking behavior. The material then develops into detailed circuit and architectural analysis of specific clock generation blocks. This includes circuits and architectures of PLLs with high power supply noise immunity and digital PLL architectures where the loop filter is digitized. Methods of generating low-spurious sampling clocks for discrete-time analog blocks are then examined.

Low-Power Digital VLSI Design: Circuits and Systems addresses both process technologies and device modeling. Power dissipation in CMOS circuits, several practical circuit examples, and low-power techniques are discussed. Low-voltage issues for digital CMOS and BiCMOS circuits are emphasized. The book also provides an extensive study of advanced CMOS subsystem design. A low-power design methodology is presented with various power minimization techniques at the circuit, logic, architecture and algorithm levels.

Log-domain and translinear filters provide a competitive alternative to the challenges of ever increasing low-voltage, low-power and high frequency demands in the area of continuous-time filters. Since translinear filters are fundamentally large-signal linear, they are capable of realizing a large dynamic range in combination with excellent tunability characteristics. Large-signal linearity is achieved by exploiting the accurate exponential behavior of the bipolar transistor or the subthreshold MOS transistor. A generalization of the dynamic translinear principle exploiting the square law behavior of the MOS transistor is theoretically possible, but not practically relevant.