SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware Design and Modeling by Stuart SutherlandEnglish | PDF | 2006 | 437 Pages | ISBN : 0387333991 | 3.29 MB
SystemVerilog is a rich set of extensions to the Verilog Hardware Description Language (Verilog HDL). SystemVerilog for Design describes the correct usage of these extensions for modeling digital designs. These important extensions enable the representation of complex digital logic in concise, accurate, and reusable hardware models. All key SystemVerilog design features are presented, such as declaration spaces, two-state data types, enumerated types, user-defined types, structures, unions, interfaces, and RTL coding extensions.