Active Hdl

Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, advances VHDL’s verification capabilities with Active-HDL, version 13.0. This latest release introduces support for VHDL-2019 protected types with generics, composites of protected types, pointers to objects of protected types and composition with protected types.

Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has enhanced Active-HDL to support new features within VHDL-2019 (IEEE 1076-2019). These features simplify the language, lift certain restrictions that were present in earlier versions and introduce new application programming interfaces (APIs).

From an expert with 15+ years experience. Core Design principles for VLSI, Soc, Processor and FPGA. VHDL alternative.

Cadence Design Systems, Inc. , the leader in global electronic design innovation, has unveiled Stratus High-Level Synthesis (HLS) versions 20.10.100 - 22.02.001 is the first high-level synthesis platform for use across your entire SoC design.

Cadence Design Systems, Inc. has released an update (HF025) to OrCAD Capture, PSpice Designer and PCB Designer 17.2-2016. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.

Cadence Design Systems, Inc. has released Cadence OrCAD X Design Platform 2024 (24.10.001) . This release includes fixes to various user-reported issues from the previous release, providing an overall more stable experience.