Automatic Analog IC Sizing And Optimization Constrained With Pvt Corners And Layout Effects

Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects (Repost)

Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects By Nuno Lourenço, Ricardo Martins, Nuno Horta
English | PDF | 2017 | 199 Pages | ISBN : 3319420364 | 13.88 MB

This book introduces readers to a variety of tools for automatic analog integrated circuit (IC) sizing and optimization. The authors provide a historical perspective on the early methods proposed to tackle automatic analog circuit sizing, with emphasis on the methodologies to size and optimize the circuit, and on the methodologies to estimate the circuit’s performance.