Esd

The challenges associated with the design and implementation of Electrostatic Discharge (ESD) protection circuits are becoming increasingly complex as technology is scaled well into nano-metric regime. Traditional approaches of ESD design may not be adequate as the ESD damages occur at successively lower voltages in nano-metric dimensions. There are several challenges that must be met in order to design robust ESD circuits today. Due to technology scaling and proliferation of automated handling, ESD failures in ICs caused by Charged Device Model (CDM) are increasing. CDM discharges can cause latent damages which could degrade and eventually lead to definite failures in the ICs. The ESD protection design for current and future sub-65nm CMOS circuits is a challenge for high I/O count, multiple power domains and flip-chip products.

Electrostatic discharge (ESD) continues to impact semiconductor manufacturing, semiconductor components and systems, as technologies scale from micro- to nano electronics.

A comprehensive and in-depth review of analog circuit layout, schematic architecture, device, power network and ESD design
This book will provide a balanced overview of analog circuit design layout, analog circuit schematic development, architecture of chips, and ESD design. It will start at an introductory level and will bring the reader right up to the state-of-the-art.