Aldec

Aldec, Inc., a industry-leading Electronic Design Automation (EDA) company delivering innovative design creation, simulation and verification solutions to assist in the development of complex FPGA, ASIC, SoC and embedded system designs, announces the latest release of its mixed-language, advanced verification platform, Riviera-PRO 2014.06. This release extends Riviera-PRO’s already powerful visual mapping capabilities for UVM verification environments.

Aldec, Inc. announced of Active-HDL version 9.1, an award-winning HDL-based FPGA Design and Simulation solution that supports the newest FPGA devices available from all leading FPGA vendors.

Aldec, Inc., announces the latest release of its mixed-language, advanced verification platform, Riviera-PRO 2014.10. This release of Riviera-PRO delivers speed and efficiency to the verification process by enhancing coverage metrics. Riviera-PRO has long supported UCIS-compatible coverage databases, and the latest release enables a new approach by linking requirements-based, user-defined test plan with coverage metrics.

Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has launched ALINT-PRO 2021.09 is design rule checking (DRC) tool, which decreases development time dramatically by identifying design issues early in the development schedule.

Active-HDL is a Windows based integrated FPGA Design and Simulation solution. Active-HDL includes a full HDL graphical design tool suite and RTL/gate-level mixed-language Simulator.

Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has enhanced Active-HDL to support new features within VHDL-2019 (IEEE 1076-2019). These features simplify the language, lift certain restrictions that were present in earlier versions and introduce new application programming interfaces (APIs).

Aldec, Inc., announces the latest release of its mixed-language FPGA design platform, Active-HDL 10.1. Popular with designers for more than 15 years for FPGA design entry and simulation due to its award-winning and intuitive GUI and high performance simulator, Active-HDL now offers support for 64-bit simulation to meet the growing demand of simulation of larger designs.

Aldec, Inc., announces the latest release of its mixed-language FPGA design platform, Active-HDL 10.1. Popular with designers for more than 15 years for FPGA design entry and simulation due to its award-winning and intuitive GUI and high performance simulator, Active-HDL now offers support for 64-bit simulation to meet the growing demand of simulation of larger designs.

Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, advances VHDL’s verification capabilities with Active-HDL, version 13.0. This latest release introduces support for VHDL-2019 protected types with generics, composites of protected types, pointers to objects of protected types and composition with protected types.

Riviera-PRO is a high-performance verification platform for ASIC and FPGA design teams, equipped with mixed-language simulation engine and advanced debugging tools. Riviera-PRO supports Electronic System Level (ESL) Verification with SystemC and SystemVerilog, Assertions Based Verification (ABV), Transaction Level Modeling (TLM) and VHDL/Verilog Linting. Riviera-PRO works in command line mode for maximum speed and is also equipped with a powerful GUI for enhanced editing, tracing, and debugging.