High-Level Verification: Methods and Tools for Verification of System-Level Designs by Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta English | 2011 | ISBN: 1441993584 | 180 pages | PDF | 2.04 MB
High-Level Modeling and Synthesis of Analog Integrated Systems by Ewout S.J. Martens, Georges Gielen English | 2008 | ISBN: 1402068018 | 300 pages | PDF | 1.75 MB
High-Level Synthesis: From Algorithm to Digital Circuit by Philippe Coussy English | PDF | 2008 | 307 Pages | ISBN : 1402085877 | 11.58 MB
The successful usage of Hardware Description Languages like VHDL and Verilog in design flows is mainly due to the availability of efficient synthesis methods and tools that enable the translation of RTL designs into optimized gate-level implementations. Many expect that the same approach could be effectively adapted at higher levels of abstraction. In the SoCs context, the traditional IC design methodology relying on EDA tools used in a two stages design flow - a VHDL/Verilog RTL specification, followed by logical and physical synthesis - is indeed no more suitable.
High-Level Synthesis: from Algorithm to Digital Circuit by Philippe Coussy, Adam Morawiec Sрrіnger; 1 edition | English | 2008 | ISBN: 1402085877 | 316 pages | PDF | 10.18 MB
Georges Gielen, "High-Level Modeling and Synthesis of Analog Integrated Systems" English | 2008 | pages: 287 | ISBN: 1402068018, 9048177316 | PDF | 1,9 mb
Zheng Wang and Anupam Chattopadhyay, "High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip" English | ISBN: 9811010722 | 2017 | 220 pages | PDF, EPUB | 19 MB