Multi Core

Fuzzy Logic Based Power-Efficient Real-Time Multi-Core System  eBooks & eLearning

Posted by arundhati at Dec. 10, 2016
Fuzzy Logic Based Power-Efficient Real-Time Multi-Core System

Jameel Ahmed, Mohammed Yakoob Siyal, "Fuzzy Logic Based Power-Efficient Real-Time Multi-Core System"
2016 | ISBN-10: 9811031193 | 62 pages | PDF | 2 MB

Fuzzy Logic Based Power-Efficient Real-Time Multi-Core System  eBooks & eLearning

Posted by arundhati at Feb. 6, 2017
Fuzzy Logic Based Power-Efficient Real-Time Multi-Core System

Jameel Ahmed, Mohammed Yakoob Siyal, "Fuzzy Logic Based Power-Efficient Real-Time Multi-Core System"
2017 | ISBN-10: 9811031193 | 62pages | PDF | 2 MB
Hardware/Software Co-design for Heterogeneous Multi-core Platforms: The hArtes Toolchain (repost)

Hardware/Software Co-design for Heterogeneous Multi-core Platforms: The hArtes Toolchain by Koen Bertels
English | 2012 | ISBN: 940071405X | 253 pages | PDF | 10,2 MB

HW/SW Co-Design for Heterogeneous Multi-Core Platforms describes the results and outcome of the FP6 project which focuses on the development of an integrated tool chain targeting a heterogeneous multi core platform comprising of a general purpose processor (ARM or powerPC), a DSP (the diopsis) and an FPGA.

A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof  eBooks & eLearning

Posted by interes at Feb. 19, 2015
A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof

A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof by Mikhail Kovalev and Silvia Melitta Müller
English | 2014 | ISBN: 3319139053 | 352 pages | PDF | 5,5 MB

Intel Threading Building Blocks: Outfitting C++ for Multi-core Processor Parallelism  eBooks & eLearning

Posted by ButcherBird at Oct. 29, 2007
Intel Threading Building Blocks: Outfitting C++ for Multi-core Processor Parallelism

James Reinders, "Intel Threading Building Blocks: Outfitting C++ for Multi-core Processor Parallelism"
O'Reilly Media, Inc. | ISBN: 0596514808 | 332 Pages | PDF | 2.5 MB

Multi-core chips from Intel and AMD offer a dramatic boost in speed and responsiveness, and plenty of opportunities for multiprocessing on ordinary desktop computers. But they also present a challenge: More than ever, multithreading is a requirement for good performance. This guide explains how to maximize the benefits of these processors through a portable C++ library that works on Windows, Linux, Macintosh, and Unix systems. With it, you'll learn how to use Intel Threading Building Blocks (TBB) effectively for parallel programming – without having to be a threading expert.

A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof  eBooks & eLearning

Posted by interes at Oct. 13, 2019
A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof

A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof by Mikhail Kovalev and Silvia Melitta Müller
English | 2014 | ISBN: 3319139053 | 352 pages | PDF | 5,5 MB
Hardware/Software Co-design for Heterogeneous Multi-core Platforms: The hArtes Toolchain (repost)

Hardware/Software Co-design for Heterogeneous Multi-core Platforms: The hArtes Toolchain by Koen Bertels
English | 2012 | ISBN: 940071405X | 253 pages | PDF | 10,2 MB
Intel Threading Building Blocks: Outfitting C++ for Multi-core Processor Parallelism

Intel Threading Building Blocks: Outfitting C++ for Multi-core Processor Parallelism By James Reinders
2007 | 334 Pages | ISBN: 0596514808 | PDF | 3 MB
Hardware/Software Co-design for Heterogeneous Multi-core Platforms: The hArtes Toolchain

Koen Bertels, "Hardware/Software Co-design for Heterogeneous Multi-core Platforms: The hArtes Toolchain"
S,..,er | 2012 | ISBN: 940071405X | 253 pages | PDF | 10,2 MB
Hardware/Software Co-design for Heterogeneous Multi-core Platforms: The hArtes Toolchain (repost)

Koen Bertels, "Hardware/Software Co-design for Heterogeneous Multi-core Platforms: The hArtes Toolchain"
2012 | English | ISBN: 940071405X | 253 pages | PDF | 10,2 MB

HW/SW Co-Design for Heterogeneous Multi-Core Platforms describes the results and outcome of the FP6 project which focuses on the development of an integrated tool chain targeting a heterogeneous multi core platform comprising of a general purpose processor (ARM or powerPC), a DSP (the diopsis) and an FPGA.