Silicon Chip 2008

Substrate Noise Coupling in RFICs addresses substrate noise coupling in RF and mixed signal ICs when used in a system on chip (SoC) containing digital ICs as well. This trend of integrating RF, mixed signal ICs with large digital ICs is found in many of today's commercial ICs such as single chip Wi-Fi or Bluetooth solutions and is expected to grow rapidly in the future. The book reports modeling and simulation techniques for substrate noise coupling effects in RFICs and introduces isolation structures and design guides to mitigate such effects with the ultimate goal of enhancing the yield of RF and mixed signal SoCs . This is particularly critical when process feature sizes scale down to the nano meter range.

IAR Systems recently released new version of Embedded Workbench for 8051. This release adds new device support, and improvement in C-STAT.

Altera, now part of Intel, announced the production release of the new Quartus Prime Pro design software, which further accelerates FPGA design performance and design team productivity.

The challenges associated with the design and implementation of Electrostatic Discharge (ESD) protection circuits are becoming increasingly complex as technology is scaled well into nano-metric regime. Traditional approaches of ESD design may not be adequate as the ESD damages occur at successively lower voltages in nano-metric dimensions. There are several challenges that must be met in order to design robust ESD circuits today. Due to technology scaling and proliferation of automated handling, ESD failures in ICs caused by Charged Device Model (CDM) are increasing. CDM discharges can cause latent damages which could degrade and eventually lead to definite failures in the ICs. The ESD protection design for current and future sub-65nm CMOS circuits is a challenge for high I/O count, multiple power domains and flip-chip products.