Analysis and Design of Networks-on-Chip Under High Process Variation
Springer | Circuits & Systems | January 16, 2016 | ISBN-10: 3319257641 | 141 pages | pdf | 6.45 mb
by Rabab Ezz-Eldin (Author), Magdy Ali El-Moursy (Author), Hesham F. A. Hamed (Author)
Demonstrates the impact of process variation on Networks-on-Chip of different topologies
Includes an overview of the synchronous clocking scheme, clock distribution network, main building blocks in asynchronous NoC design, handshake protocols, data encoding, asynchronous protocol converters and routing algorithms
Describes a novel adaptive routing algorithm for asynchronous NoC designs, which selects the appropriate output path based on process variation and congestion