Systemc

SystemC provides a robust set of extensions to the C++ language that enables rapid development of complex models of hardware and software systems. The authors focus on practical use of the language for modeling real systems, showing:

SystemC provides a robust set of extensions to the C++ language that enables rapid development of complex models of hardware and software systems. The authors focus on practical use of the language for modeling real systems, showing:

SystemC has received a wide acceptance by users and tool vendors as the next generation system description language in order to deal with higher levels of abstraction for complex SoC designs. SystemC Methodologies and Applications gives a comprehensive survey on the state of the art of SystemC in industry and research. Organised into 11 self-contained chapters, selected SystemC experts present their approaches in the domains of
-modelling,
-analysis,
-synthesis.
Their contributions range from mixed signal and discrete system to embedded software. The chapters give a broad overview of recent advances in SystemC methodologies and applications and are mainly based on presentations given at the European SystemC User Group meetings.

I am honored and delighted to write the foreword to this very first book about SystemC. It is now an excellent time to summarize what SystemC really is and what it can be used for. The main message in the area of design in the 2001 International Te- nologyRoadmapfor Semiconductors (ITRS) isthat“cost ofdesign is the greatest threat to the continuation ofthe semiconductor roadmap.

Currently employed at STMicroelectronics, Transactional-Level Modeling (TLM) puts forward a novel SoC design methodology beyond RTL with measured improvements of productivity and first time silicon success.

"As chip size and complexity continues to grow exponentially, the challenges of functional verification are becoming a critical issue in the electronics industry. It is now commonly heard that logical errors missed during functional verification are the most common cause of chip re-spins, and that the costs associated with functional verification are now outweighing the costs of chip design. To cope with these challenges engineers are increasingly relying on new design and verification methodologies and languages. Transaction-based design and verification, constrained random stimulus generation, functional coverage analysis, and assertion-based verification are all techniques that advanced design and verification teams routinely use today. Engineers are also increasingly turning to design and verification models based on C/C++ and SystemC in order to build more abstract, higher performance hardware and software models and to escape the limitations of RTL HDLs. This new book, Advanced Verification Techniques, provides specific guidance for these advanced verification techniques. The book includes realistic examples and shows how SystemC and SCV can be applied to a variety of advanced design and verification tasks."