Rtl

Cadence Design Systems, Inc. , the leader in global electronic design innovation, has unveiled Cadence Joules RTL Power Solution 21.16.000-ISR6 Hotfix. This solution delivering time based RTL power analysis with system-level runtimes and capacity, as well as high-quality estimates of gates and wires based on production implementation technology.

Cadence Design Systems, Inc. , the leader in global electronic design innovation, has unveiled Cadence Joules RTL Power Solution 19.10.000 - 21.14.000. This solution delivering time based RTL power analysis with system-level runtimes and capacity, as well as high-quality estimates of gates and wires based on production implementation technology.

Mentor Graphics Corporation, a world leader in electronic hardware and software design solutions, providing products and consulting services, has presented Precision RTL Plus\Synthesis 2015.2, is a synthesis platform that maximizes the performance of both, existing programmable logic devices (CPLDs and FPGAs) and next-generation, multi-million gate field programmable system-on-chip (FPSoC) devices.

Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has launched ALINT-PRO 2021.09 is design rule checking (DRC) tool, which decreases development time dramatically by identifying design issues early in the development schedule.

Cadence Design Systems, Inc. has unveiled the Cadence Genus Synthesis Solution 19.10.000 - 21.12.000, its next-generation register-transfer level (RTL) synthesis and physical synthesis engine, to address the productivity challenges faced by RTL designers.

Cadence Design Systems, Inc. has released Genus Synthesis Solution 21.17.000-ISR7, its next-generation register-transfer level (RTL) synthesis and physical synthesis engine, to address the productivity challenges faced by RTL designers.

Synopsys, Inc., the world leader in semiconductor design software, has unveiled Synopsys SpyGlass vP-2019.06 SP1.1. Using many advanced algorithms and analysis techniques, this platform provides designers with insight about their design, early in the process at RTL. It functions like an interactive guidance system for design engineers and managers, finding the fastest and least expensive path to implementation for complex SoCs.

Synopsys, Inc., the world leader in semiconductor design software, has unveiled Synopsys SpyGlass vQ-2020.03 SP2-3 – Early Design Analysis Tools Enable Efficient Static Verification of FPGA Designs.

Synopsys, Inc., the technology leader for complex IC design, has unveiled VC Static Tools vS-2021.09, part of the Synopsys Verification Continuum Platform. This tools enable designers and verification engineers to quickly analyze and check RTL designs very early in the design flow, with no need for complex setup, testbenches or stimulus.

Cadence Design Systems, Inc. , the leader in global electronic design innovation, has unveiled INNOVUS 18.10.000 is part of the broader Cadence digital and signoff suite, which provides customers with an integrated full flow, delivering a predictable path to design closure and also supports Cadence’s Intelligent System Design strategy, accelerating SoC design excellence.